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Vectorization: The Rise of Parallelism

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In this article, we discuss the new challenges in the financial markets that have been driven by changes in market structure and regulations and accounting rules like Basel IIIEMIR, Dodd Frank, MiFID II, Solvency II, IFRS 13, IRFS 9, and FRTB have increased demand for higher performance risk and analytics. Problems like XVA require orders of magnitude more calculations for accurate results. This demand for higher performance has put a focus on how to get the most out of the latest generation of hardware.

For the past decade, Moore’s law has continued to prevail, but while chip makers have continued to pack more transistors into every square inch of silicon, the focus of innovation has moved away from greater clock speeds and towards multicore and many core architectures.

We discuss multi core chip design, the deployment of SIMD and implementing vectorization. At the same time that the multi core chip design has given rise to task parallelism in software design, chipmakers have also been increasing using a second type of parallelism - instruction level parallelism. Alongside the trend to increase core count, the width of SIMD (single instruction, multiple data) registers has been steadily increasing.  The software changes required to exploit instruction level parallelism are known as ‘vectorization’. Multi-threading and vectorization are powerful tools on their own, but only by combining them can performance be maximized. Trading parties often agree to mitigate counterparty risk by requiring collateral be posted to cover losses in the event of default. Collateral agreements can take a variety of forms, here we present a simplified version with some of the most common features.

In this article, we discuss the new challenges in the financial markets that have been driven by changes in market structure and regulations and accounting rules like Basel IIIEMIR, Dodd Frank, MiFID II, Solvency II, IFRS 13, IRFS 9, and FRTB have increased demand for higher performance risk and analytics. Problems like XVA require orders of magnitude more calculations for accurate results. This demand for higher performance has put a focus on how to get the most out of the latest generation of hardware.

For the past decade, Moore’s law has continued to prevail, but while chip makers have continued to pack more transistors into every square inch of silicon, the focus of innovation has moved away from greater clock speeds and towards multicore and many core architectures.

We discuss multi core chip design, the deployment of SIMD and implementing vectorization. At the same time as the multi core chip design has given rise to task parallelism in software design, chipmakers have also been increasing using a second type of parallelism - instruction level parallelism. Alongside the trend to increase core count, the width of SIMD (single instruction, multiple data) registers has been steadily increasing. The software changes required to exploit instruction level parallelism are known as ‘vectorization’. Multi-threading and vectorization are powerful tools on their own, but only by combining them can performance be maximized. Trading parties often agree to mitigate counterparty risk by requiring collateral be posted to cover losses in the event of default. Collateral agreements can take a variety of forms, here we present a simplified version with some of the most common features.

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